The present invention relates to a phase locked loop and a method for adjusting the frequency and/or the phase in the phase locked loop.
A purpose of a phase locked loop (PLL) is to measure the phase difference between a reference signal and a variable signal from a controllable oscillator implemented in the PLL and to use that phase difference to make a frequency adjustment to the variable signal. A PLL which fulfills this purpose is described in the prior art EP 1 443 653 A1. The PLL shown in the prior art is a type-II all-digital phase locked loop. It comprises a proportional loop gain block, a linear loop gain block and a time-to-digital converter. The time-to-digital converter is implemented in such a way that the phase difference between the digitally controlled oscillator frequency and reference frequency is multiplied with an inverse period to carry out a normalization of the measured phase difference. This normalized phase difference is then used to adjust the loop gain.
The application of the PLL for clock and data recovery in a serial data link receiver requires the capability to adjust the output phase of the PLL in discrete phase steps. The embodiment of the PLL described in EP 1 443 653 does not show this feature. A further helpful feature is to monitor the jitter of the PLL, which however is also not disclosed in EP 1 443 653.